1. Technical Field
Embodiment discussed herein relate generally to microelectronic circuit devices and more particularly, but to exclusively, to evaluating the operation of integrated circuitry using a general purpose interface.
2. Background Art
Currently, typical laptop, tablet, smartphone or other systems comprise a system-on-chip (SoC) and/or other integrated circuits (ICs) that are debugged and tested via a JTAG (or cJTAG) interface. Typically, it is desirable to send debug traces from system circuitry (e.g., a SoC or other IC) via a high-speed interface that exists on the system. The JTAG test data out (TDO) pin can also be used to send output debug traces, albeit at a lower data rate. Typically, the IEEE-1149.1 JTAG interface runs at about 100 MHz. The IEEE standards committee has also developed a 2-pin JTAG interface via IEEE-1149.7 standard (also known as compact JTAG or cJTAG) which uses TMSc and TCKc signals for debug and test. Since the data rate of a JTAG interface is typically around 100 Mhz and most trace requirements are much higher than the JTAG data rate, the trace is conventionally sent out of the system via a dedicated high-speed serial trace port. However, as devices trend toward “closed chassis” solutions having fewer external connectors, there is an increasing demand to eliminate external ports that are specific to supporting test, debug and/or trace information.